Adaptive Error-Prediction Aging Sensor for On-Line Monitoring of Performance Errors

This paper presents a new aging sensor architecture for error prediction of performance errors in synchronous digital circuits. The aging sensor is based on a new flip-flop with built-in logic that predicts the errors by monitoring long-term performance degradation of CMOS digital systems. The main advantage is that the sensor’s long-term degradation effects increase its sensitivity to performance error prediction. Moreover, the reduction of the power-supply voltage (V) and the increase of the temperature (T) also make the sensor to increase its sensitivity, making the sensor to adapt its monitoring capability with aging and VT variations. Performance failure prediction is implemented by the detection of late transitions at flip-flop data input, caused by aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, or even by a worst-case operating condition (namely, V and/or T). Extensive SPICE simulations allowed achieving a new flip-flop with additional aging sensor capability, however with negligible performance degradation, because the sensing circuitry is out of the signal path. Simulation results are presented for two CMOS technologies (65nm and 22nm), using Berkeley Predictive Technology Models (PTM). It is shown that PVTA (Process, power supply Voltage, Temperature and Aging) variations on the sensor enhance error prediction capability. Keywords-aging sensor; performance failure prediction; NBTI; on-line monitoring.